Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors

Abstract

Interface and near oxide traps in small gate area MOS transistors (gate area ,1 mm2) lead to RTS noise which implies the emergence of noisy pixels in CMOS image sensors. To reduce this noise, two simple and efficient layout techniques of custom transistors have been imagined. These techniques have been successfully implemented in an image sensor test chip fabricated in a 0.35 mm CMOS image sensor process. Experimental results demonstrate a significant reduction of the noisy pixels for the two different techniques.