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Modeling and verification of memory architectures with AADL and REAL

Rubini, Stéphane and Singhoff, Frank and Hugues, Jérôme Modeling and verification of memory architectures with AADL and REAL. (2011) In: Sixth IEEE International workshop UML and AADL - UML&AADL'2011, 27 April 2011 - 29 April 2011 (Las Vegas, United States).

(Document in English)

PDF (Author's version) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader

Official URL: http://dx.doi.org/10.1109/ICECCS.2011.40


Real-Time Embedded systems must respect a wide range of non-functional properties, including safety, respect of deadlines, power or memory consumption. We note that correct hardware resource dimensioning requires taking into account the impact of the whole software, both the user code and the underlying runtime environment. AADL allows one to precisely capture all of them. In this article, we evaluate the AADL modeling to define memory architectures, and then verification rules to assess that the memory is correctly dimensioned. We use the REAL domain-specific language to express memory requirements (such as layout or size) and then validate them on a case-study using the VxWorks real-time kernel.

Item Type:Conference or Workshop Item (Paper)
Additional Information:Thanks to the Institute of Electrical and Electronics Engineers (IEEE). The original PDF can be found on the IEEE website: http://ieeexplore.ieee.org/
Audience (conference):International conference proceedings
Uncontrolled Keywords:
Institution:Université de Toulouse > Institut Supérieur de l'Aéronautique et de l'Espace - ISAE-SUPAERO (FRANCE)
Other partners > Université de Bretagne Occidentale - UBO (FRANCE)
Laboratory name:
Deposited On:03 May 2011 12:03

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