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Tightness and Computation Assessment of Worst-Case Delay Bounds in Wormhole Networks-On-Chip

Giroudot, Frédéric and Mifdaoui, Ahlem Tightness and Computation Assessment of Worst-Case Delay Bounds in Wormhole Networks-On-Chip. (2019) In: 27th International Conference on Real-Time Networks and Systems (RTNS 2019), 6 November 2019 - 8 November 2019 (Toulouse, France).

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Official URL: https://doi.org/10.1145/3356401.3356408


This paper addresses the problem of worst-case timing analysis in wormhole Networks-On-Chip (NoCs). We consider our previous work [5] for computing maximum delay bounds using Network Calculus, called the Buffer-Aware Worst-case Timing Analysis (BATA). The latter allows the computation of delay bounds for a large panel of wormhole NoCs, e.g., handling priority-sharing, Virtual Channel Sharing and buffer backpressure.In this paper, we provide further insights into the tightness and computation issues of the worst-case delay bounds yielded by BATA. Our assessment shows that the gap between the computed delay bounds and the worst-case simulation results is reasonably small (70% tightness on average). Furthermore, BATA provides good delay bounds for medium-scale configurations within less than one hour. Finally, we evaluate the yielded improvements with BATA for a realistic use-case against a recent state-of-the-art approach. This evaluation shows the applicability of BATA under more general assumptions and the impact of such a feature on the tightness and computation time.

Item Type:Conference or Workshop Item (Paper)
HAL Id:hal-02482683
Audience (conference):International conference proceedings
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Institution:Université de Toulouse > Institut Supérieur de l'Aéronautique et de l'Espace - ISAE-SUPAERO (FRANCE)
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Deposited On:18 Feb 2020 10:19

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