Design Impact on Charge Transfer Inefficiency of Surface CCD on CMOS Devices: TCAD and Characterization Study

Abstract

This work presents a study of design optimization of CCD on CMOS devices, in order to minimize the Charge Transfer Inefficiency (CTI). To achieve this goal, 3D Technology Computer Aided Design (TCAD) simulations with a trap model at silicon–oxide interface were conducted, and measurements on two test chips manufactured on two different foundries were performed. TCAD simulations predict trends in agreement with measurements, but trap models at STI and gate oxides should be adapted accordingly to the technology used. Some design variations show results depending on the technology chosen, and the best CTI reduction is obtained with an increase of Pwell inclusion over STI edges.