Towards a unified approach for worst-case analysis of Tilera-like and KalRay-like NoC architectures

Abstract

n this paper, we consider two Network-on-Chip (NoC) architectures used within commercially available many-core systems, namely Tilera TILE64 which implements flow regulation within routers and KalRay MPPA 256 which implements flow regulation in source nodes. The Worst-Case Traversal Time (WCTT) on the NoC has to be bounded for real-time applications, and buffers should never overflow. Different worst-case analysis approaches have been proposed for each of these NoC architectures. However, no general worst-case analysis supporting both NoC architectures exists in the literature and most approaches are specific to one of the studied NoC. In this paper, we propose to use Recursive Calculus (RC) method for Tilera and KalRay. Furthermore, we compare the performances on a preliminary case study, in terms of WCTT and required buffer capacity. It allows to quantify the trade-off between delays and buffer occupancy.