Ayed, Hamdi and Ermont, Jérôme
and Scharbarg, Jean-Luc
and Fraboul, Christian
Extended recursive analysis for tilera tile64 NoC architectures: towards inter-NoC delay analysis.
(2017)
SIGBED Review, 14 (3). 35-37. ISSN 1551-3688
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(Document in English)
PDF (Author's version) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader 192kB |
Official URL: https://doi.org/10.1145/3166227.3166232
Abstract
A heterogeneous network, where a switched-Ethernet backbone, e.g. AFDX, interconnects several end systems based on Network-on-Chip (NoC), is a promising candidate to build new avionics architectures. When using such a heterogeneous network for real-time applications, a global worst-case traversal time (WCTT) analysis is needed. In this short paper we focus on the intra-NoC communication on a Tilera TILE64-like NoC. First, we extend the Recursive Calculus (RC) to achieve tighter intra-NoC WCTT. Then, we explain how this intra-NoC WCTT analysis could be used in a compositional manner for the end-to-end inter-NoC delay analysis.
Item Type: | Article |
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Additional Information: | Thanks to Association for Computing Machinery (ACM) editor. The original PDF of the article can be found at TSIGBED Review website : https://dl.acm.org/citation.cfm?doid=3166227.3166232 |
HAL Id: | hal-02001611 |
Audience (journal): | International peer-reviewed journal |
Uncontrolled Keywords: | |
Institution: | French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE) Université de Toulouse > Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE) Université de Toulouse > Université Toulouse III - Paul Sabatier - UT3 (FRANCE) Université de Toulouse > Université Toulouse - Jean Jaurès - UT2J (FRANCE) Université de Toulouse > Université Toulouse 1 Capitole - UT1 (FRANCE) |
Laboratory name: | |
Statistics: | download |
Deposited On: | 09 Jan 2019 14:03 |
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