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FPGA based hardware acceleration of a BRIEF correlator module for a monocular SLAM application

Brenot, François and Piat, Jonathan and Fillatreau, Philippe FPGA based hardware acceleration of a BRIEF correlator module for a monocular SLAM application. (2016) In: 10th International Conference on Distributed Smart Camera (ICDSC 2016), 12 September 2016 - 15 September 2016 (Paris, France).

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Official URL: https://doi.org/10.1145/2967413.2967426


Robot localization is a mandatory ability for the robot to navigate the world. Solving the SLAM (Simultaneous Localization and Mapping) allows the robot to both localize itself in the environment while building a map of its surrounding. Vision-based SLAM uses one or more camera as the main source of information. The SLAM involves a large computation load on its own and using vision involves even more complexity that does not scale well. This increasing complexity makes it hard to solve in real-time for applications where the SLAM high rate and low latency are inherent constraints (Advanced Drivers Assistance Systems). To help robots solve the SLAM in real-time we propose to build a vision-core that aims at processing the pixel stream coming from the camera in a vision front-end that let a SLAM method work only with high-level features extracted from the image. This paper describes the implementation on FPGA of a core that computes the BRIEF descriptor from a camera output. We also present the implementation of the correlation method for this descriptor for the tracking in an image sequence. This core is then tested in an embedded SLAM application with good speed-up.

Item Type:Conference or Workshop Item (Paper)
HAL Id:hal-02053200
Audience (conference):International conference proceedings
Uncontrolled Keywords:
Institution:French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE)
Université de Toulouse > Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)
Laboratory name:
Deposited On:31 Jan 2019 13:30

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