Ghfiri, Chaimae
and Durier, André and Boyer, Alexandre and Ben Dhia, Sonia
A new methodology to extract the ICEM-CE internal activity block of a FPGA.
(2017)
In: EMC Europe, 4 September 2017 - 8 September 2017 (Angers, France).
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(Document in English)
PDF (Author's version) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader 340kB |
Official URL: http://dx.doi.org/10.1109/EMCEurope.2017.8094792
Abstract
This paper describes a new methodology of construction of the internal activity block of an ICEM-CE model of an FPGA based on a predictive approach using the estimation tools of the dynamic power and the static timing proposed by the manufacturer of the integrated circuit.
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| Additional Information: | Thanks to IEEE. The document original is available on IEEE Xplore : http://dx.doi.org/10.1109/EMCEurope.2017.8094792. ©2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
| HAL Id: | hal-01661809 |
| Audience (conference): | International conference proceedings |
| Uncontrolled Keywords: | |
| Institution: | French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE) Other partners > IRT Saint Exupéry - Institut de Recherche Technologique (FRANCE) |
| Laboratory name: | |
| Funders: | IRT Saint-Exupery - Airbus Operations - Airbus Group Innovations - Continental Automotive France - Hirex Engineering - Nexio - Safran Electrical & Power - Thales Alenia Space France - Thales Avionics - French National Agency for Research (ANR) |
| Statistics: | download |
| Deposited On: | 12 Dec 2017 10:39 |
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