An experiment on exploiting virtual platforms for the development of embedded equipments

Abstract

Virtual engineering methods and tools based on simulation have become a privileged means to reduce time-to-market and product cost. However, design and verification activities still need to be im-proved to manage the ever increasing complexity of electronic products and their interactions with hetero-geneous environments. In particular, an important challenge is to master the real time properties of the product composed of interacting hardware and soft-ware components. In this paper we propose a pragmatic approach to use virtual platforms to verify gradually and accurately the properties of a system under design. We illustrate the approach on an example.