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Performance Verification for ESL Design Methodology from AADL Models

Gaudron, Matthieu and Bois, Guy and Hugues, Jérôme and Monteiro, Fellipe Performance Verification for ESL Design Methodology from AADL Models. (2016) In: International Symposium on Rapid System Prototyping (RSP), 8 October 2015 - 9 October 2015 (Amsterdam, Netherlands).

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Official URL: http://dx.doi.org/10.1109/RSP.2015.7416543


One of the key issues to ensure high-quality designs is the verification methodology. The typical verification methodology used for RTL design is based on the V diagram. In this article we work at higher levels of abstraction (named ESL) by focusing on the performance verification process. A sub- system and its interconnected components are modeled with AADL. AADL also contains constructs for modeling both software and hardware components. Through the ESL virtual platform SpaceStudioTM, we can rapidly estimate the performance on different architectures. This performance verification flow has been experimented on a Motion-JPEG video decoder application for video thumbnails that targets a Xilinx Zynq-7000 platform.

Item Type:Conference or Workshop Item (Paper)
Additional Information:ISBN 978-1-4673-8276-2/15
Audience (conference):International conference proceedings
Uncontrolled Keywords:
Institution:Other partners > Ecole Polytechnique de Montréal (CANADA)
Université de Toulouse > Institut Supérieur de l'Aéronautique et de l'Espace - ISAE-SUPAERO (FRANCE)
Other partners > Space Codesign Systems, Inc. (CANADA)
Laboratory name:
Deposited On:18 Jan 2016 10:33

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