Influence of Transfer Gate Design and Bias on the Radiation Hardness of Pinned Photodiode CMOS Image Sensors

Abstract

The effects of Cobalt 60 gamma-ray irradiation on Pinned Photodiode (PPD) CMOS Image Sensors (CIS) are investigated by comparing the Total Ionizing Dose (TID) response of several Transfer Gate (TG) and PPD designs manufactured using a 180 nm CIS process. The TID induced variations of Charge Transfer Efficiency (CTE), pinning voltage, Equilibrium Full Well Capacity (EFWC), Full Well Capacity (FWC) and dark current measured on the different pixel designs lead to the conclusion that only three degradation sources are responsible for all the observed radiation effects: the Pre-Metal Dielectric (PMD) positive trapped charge, the TG sidewall spacer positive trapped charge and, with less influence, the TG channel Shallow Trench Isolation (STI) trapped charge. The different FWC evolutions with TID presented here are in very good agreement with a recently proposed analytical model. This work also demonstrates that the peripheral STI is not responsible for the observed degradations and thus that the enclosed layout TG design does not improve the radiation hardness of PPD CIS. The results of this study also lead to the conclusion that the TG OFF voltage bias during irradiation has no influence on the radiation effects. Alternative design and process solutions to improve the radiation hardness of PPD CIS are discussed.