Monitoring On-line Timing Information to Support Mixed-Critical Workloads

Abstract

Many/multi-cores architectures provide tremendous increase in computation power, increasing the possibility of executing additional tasks on the system. In critical embedded systems, e.g. aeronautical systems, the uncertainty of the non-uniform and concurrent memory access scheme prohibits the full utilization of the system potentials. Classical Worst Case Execution Time (WCET) estimation techniques upper bound the memory accesses -considering a fully congested memory bus - resulting in safe, but pessimistic, bounds. The proposed approach explores the increase in the system utilization by less critical tasks, while guaranteeing the safety of the critical task.