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Worst-Case Communication Overhead in a Many-Core based Shared-Memory Model

Dkhil, Amira and Louise, Stéphane and Rochange, Christine Worst-Case Communication Overhead in a Many-Core based Shared-Memory Model. (2013) In: 7th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2013), 16 October 2013 - 18 October 2013 (Sophia Antipolis, France).

(Document in English)

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With emerging many-core architectures, using on-chip shared memories is an interesting approach because it provides high bandwidth and high throughput data exchange. Such a feature is usually implemented as a multi-bus multi-banked memory. Since predicting timing behavior is key to efficient design and verification of embedded real-time systems, the question that arises is how to evaluate the access time for one memory access of a given task while others may concurrently access the same memory-bank at t the same time. In this paper, we give the answers for a subset of streaming applications modeled like CSDF Model of Computation and implemented in Kalray’s MPPA chip.

Item Type:Conference or Workshop Item (Paper)
HAL Id:hal-01239714
Audience (conference):National conference proceedings
Uncontrolled Keywords:
Institution:French research institutions > Commissariat à l'Energie Atomique et aux énergies alternatives - CEA (FRANCE)
French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE)
Université de Toulouse > Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)
Université de Toulouse > Université Toulouse III - Paul Sabatier - UT3 (FRANCE)
Université de Toulouse > Université Toulouse - Jean Jaurès - UT2J (FRANCE)
Université de Toulouse > Université Toulouse 1 Capitole - UT1 (FRANCE)
Laboratory name:
Deposited On:02 Nov 2015 10:22

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