OATAO - Open Archive Toulouse Archive Ouverte Open Access Week

parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Ungerer, Theo and Bradatsch, Christian and Gerdes, Mike and Kluge, Florian and Jahr, Ralf and Mische, Jörg and Fernandes, Joao and Zaykov, Pavel G. and Petrov, Zlatko and Böddeker, Bert and Kehr, Sebastian and Regler, Hans and Hugl, Andreas and Rochange, Christine and Ozaktas, Haluk and Cassé, Hugues and Bonenfant, Armelle and Sainrat, Pascal and Broster, Ian and Lay, Nick and George, David and Quinones, Eduardo and Panic, Milos and Abella, Jaume and Cazorla, Francisco J. and Uhrig, Sascha and Rohde, Mathias and Pyka, Arthur parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. (2013) In: 16th Euromicro Conference on Digital System Design (DSD 2013), 4 September 2013 - 6 September 2013 (Santander, Spain).

(Document in English)

PDF (Author's version) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader

Official URL: http://dx.doi.org/10.1109/DSD.2013.46


Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

Item Type:Conference or Workshop Item (Paper)
Additional Information:Thanks to IEEE editor. The definitive version is available at http://ieeexplore.ieee.org The original PDF of the article can be found at : http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6628301&tag=1
HAL Id:hal-01231740
Audience (conference):International conference proceedings
Uncontrolled Keywords:
Institution:Other partners > Barcelona Supercomputing Center – Centro Nacional de Supercomputación - BSC-CNS (SPAIN)
French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE)
Other partners > Consejo Superior de Investigaciones Científicas - CSIC (SPAIN)
Université de Toulouse > Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE)
Université de Toulouse > Université Toulouse III - Paul Sabatier - UT3 (FRANCE)
Université de Toulouse > Université Toulouse - Jean Jaurès - UT2J (FRANCE)
Université de Toulouse > Université Toulouse 1 Capitole - UT1 (FRANCE)
Other partners > Universitat Politècnica de Catalunya - UPC (SPAIN)
Other partners > DENSO (JAPAN)
Other partners > Honeywell (USA)
Other partners > Rapita System (USA)
Other partners > Technische Universität Dortmund - TU Dortmund (GERMANY)
Other partners > University of Augsburg (GERMANY)
Laboratory name:
Deposited On:26 Oct 2015 14:23

Repository Staff Only: item control page