Ungerer, Theo and Bradatsch, Christian and Gerdes, Mike and Kluge, Florian and Jahr, Ralf and Mische, Jörg and Fernandes, Joao and Zaykov, Pavel G. and Petrov, Zlatko and Böddeker, Bert and Kehr, Sebastian and Regler, Hans and Hugl, Andreas and Rochange, Christine and Ozaktas, Haluk and Cassé, Hugues and Bonenfant, Armelle and Sainrat, Pascal and Broster, Ian and Lay, Nick and George, David and Quinones, Eduardo and Panic, Milos and Abella, Jaume and Cazorla, Francisco J. and Uhrig, Sascha and Rohde, Mathias and Pyka, Arthur parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. (2013) In: 16th Euromicro Conference on Digital System Design (DSD 2013), 4 September 2013 - 6 September 2013 (Santander, Spain).
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(Document in English)
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Official URL: http://dx.doi.org/10.1109/DSD.2013.46
Abstract
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.
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