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Novel readout circuit architecture for CMOS image sensors minimizing RTS noise

Martin-Gonthier, Philippe and Magnan, Pierre Novel readout circuit architecture for CMOS image sensors minimizing RTS noise. (2011) IEEE Electron Device Letters, vol. 32 (n° 6). pp. 776 -778. ISSN 0741-3106

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Official URL: http://dx.doi.org/10.1109/LED.2011.2127442

Abstract

This letter presents a novel readout architecture and its associated readout sequence for complementary metal–oxide– semiconductor (CMOS) image sensors (CISs) based on switch biasing techniques in order to reduce noisy pixel numbers induced by in-pixel source-follower transistor random telegraph signal noise. Measurement results done on a test image sensor designed with 0.35-μm CIS technology demonstrate an efficient reduction of noisy pixel numbers without a pixel performance decrease.

Item Type:Article
Additional Information:Thanks to IEEE editor. The definitive version is available at http://ieeexplore.ieee.org/ The original PDF of the article can be found at IEEE Electron Device Letters website: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55
Audience (journal):International peer-reviewed journal
Uncontrolled Keywords:
Institution: Université de Toulouse > Institut Supérieur de l'Aéronautique et de l'Espace - ISAE
Laboratory name:
Département d'Electronique, Optronique et Signal - DEOS (Toulouse, France) - Conception d’Imageurs Matriciels Intégrés - CIMI
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Deposited By: Philippe MARTIN-GONTHIER
Deposited On:21 Jun 2011 11:39

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