OATAO - Open Archive Toulouse Archive Ouverte Open Access Week

Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors

Martin-Gonthier, Philippe and Havard, E. and Magnan, Pierre Custom transistor layout design techniques for random telegraph signal noise reduction in CMOS image sensors. (2010) IEEE Electronics Letters , vol. 46 (n° 19). pp. 1323 -1324. ISSN 0013-5194

[img]
Preview
(Document in English)

PDF (Author's version) - Requires a PDF viewer such as GSview, Xpdf or Adobe Acrobat Reader
263Kb

Official URL: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5585039&tag=1

Abstract

Interface and near oxide traps in small gate area MOS transistors (gate area ,1 mm2) lead to RTS noise which implies the emergence of noisy pixels in CMOS image sensors. To reduce this noise, two simple and efficient layout techniques of custom transistors have been imagined. These techniques have been successfully implemented in an image sensor test chip fabricated in a 0.35 mm CMOS image sensor process. Experimental results demonstrate a significant reduction of the noisy pixels for the two different techniques.

Item Type:Article
Additional Information:Thanks to IEEE editor. The definitive version is available at http://ieeexplore.ieee.org/ The original PDF of the article can be found at IEEE Electronics Letters website: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=2220
Audience (journal):International peer-reviewed journal
Uncontrolled Keywords:
Institution: Université de Toulouse > Institut Supérieur de l'Aéronautique et de l'Espace - ISAE
Laboratory name:
Département d'Electronique, Optronique et Signal - DEOS (Toulouse, France) - Conception d’Imageurs Matriciels Intégrés - CIMI
Statistics:download
Deposited By:Philippe MARTIN-GONTHIER

Repository Staff Only: item control page