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DVFS governor for HPC: Higher, Faster, Greener

Da Costa, Georges and Pierson, Jean-Marc DVFS governor for HPC: Higher, Faster, Greener. (2015) In: 23rd Euromicro International Conference on Parallel, Distributed and network-based Processing (PDP 2015), 4 March 2015 - 6 March 2015 (Turku, Finland).

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Official URL: http://dx.doi.org/10.1109/PDP.2015.73

Abstract

In High Performance Computing, being respectful of the environment is usually secondary compared to performance: The faster, the better. As Exascale computing is in the spotlight, electric power concerns arise as current exascale projects might need too much power to even boot. A recent incentive (Exascale at maximum 20MW) shows that reality is catching up with HPC center designers. Beyond classical works on hardware infrastructure or at the middleware level, we do believe that system-level solutions have great potential for energy reduction. Moreover energy-reduction has often been neglected by the HPC community that focus mainly on raw computing performance. In the literature, energy savings is achieved mainly by two means: Either processor load is the only metric taken into account to reduce processors frequency and to ensure no impact on raw performances, Or processor frequency is managed only at task level outside the critical path. In this article we show that designing and implementing a DVFS (Dynamic Voltage and Frequency Scaling) mechanism based on instantaneous system values (here network activity) can save up to 25% of energy consumption while reducing marginally performance. In several cases, reducing energy consumption also leads to an increase in performances because of the thermal budget of recent processors. This work is validated with real experiments on a Linux cluster using the NAS Parallel Benchmark (NPB).

Item Type:Conference or Workshop Item (Paper)
Additional Information:Thanks to IEEE editor. The definitive version is available at http://ieeexplore.ieee.org This papers appears in Proceedings of 23rd Euromicro International Conference on Parallel, Distributed and Network-Based Processing. 978-1-4799-8491-6 ISSN: 1066-6192 The original PDF of the article can be found at: http://ieeexplore.ieee.org/document/7092771/?reload=true&arnumber=7092771 Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
HAL Id:hal-01387826
Audience (conference):International conference proceedings
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Institution:Université de Toulouse > Institut National Polytechnique de Toulouse - INPT (FRANCE)
French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE)
Université de Toulouse > Université Toulouse III - Paul Sabatier - UPS (FRANCE)
Université de Toulouse > Université Toulouse - Jean Jaurès - UT2J (FRANCE)
Université de Toulouse > Université Toulouse 1 Capitole - UT1 (FRANCE)
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Deposited By: IRIT IRIT
Deposited On:11 Oct 2016 14:59

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