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Modeling a spacewire architecture using timed automata to compute worst-case end-to-end delays

Ermont, Jérôme and Fraboul, Christian Modeling a spacewire architecture using timed automata to compute worst-case end-to-end delays. (2013) In: 18th IEEE Conference on Emerging Technologies & Factory Automation (ETFA 2013), 10 September 2013 - 13 September 2013 (Cagliari, Italy).

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Official URL: http://dx.doi.org/10.1109/ETFA.2013.6648072

Abstract

Spacewire is a real-time communication network for use onboard satellites. It has been designed to transmit both payload and control/command data. To guarantee that communications respect the real-time constraints, designers use tools to compute the worst-case end-to-end delays. Among these tools, recursive flow analysis and Network Calculus approaches have been studied. This paper proposes to use the model-checking approach based on timed automata. A case study based on an industrial one is shown. Our approach is compared with recursive flow analysis and Network Calculus.

Item Type:Conference or Workshop Item (Paper)
Additional Information:Thanks to IEEE editor. The definitive version is available at http://ieeexplore.ieee.org The original PDF of the article can be found at : http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6648072 ISBN: 978-1-4799-0862-2
HAL Id:hal-01212888
Audience (conference):International conference proceedings
Uncontrolled Keywords:
Institution:Université de Toulouse > Institut National Polytechnique de Toulouse - INPT (FRANCE)
French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE)
Université de Toulouse > Université Toulouse III - Paul Sabatier - UPS (FRANCE)
Université de Toulouse > Université Toulouse - Jean Jaurès - UT2J (FRANCE)
Université de Toulouse > Université Toulouse 1 Capitole - UT1 (FRANCE)
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Deposited By: IRIT IRIT
Deposited On:11 Sep 2015 13:21

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