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Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets

Bourgade, Roman and Rochange, Christine and Sainrat, Pascal Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets. (2013) In: 26th International Conference on Architecture of Computing Systems - ARCS 2013, 19 February 2013 - 22 February 2013 (Prague, Czech Republic).

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Official URL: http://dx.doi.org/10.1007/978-3-642-36424-2_29

Abstract

In a multicore processor, arbitrating the shared resources so as to ensure predictable latencies for hard real-time tasks is challenging. In [1], we have introduced a two-level bus arbitration scheme that fits the needs of heterogeneous task sets, when some tasks have a higher demand to memory than others. In this paper, we show how this scheme can be used to optimise the overall utilisation of the cores while enforcing the schedulability of the whole task set. Our approach both configures the bus arbiter and maps the tasks onto the cores. Experimental results show that it reduces the global utilisation of the cores compared to the traditional round-robin scheme.

Item Type:Conference or Workshop Item (Paper)
Additional Information:Thanks to Springer editor. The definitive version is available at http://link.springer.com The original PDF of the article can be found at Springer website : http://link.springer.com/chapter/10.1007%2F978-3-642-36424-2_29/pii/S0009261400005583#
Audience (conference):International conference proceedings
Uncontrolled Keywords:
Institution:Université de Toulouse > Institut National Polytechnique de Toulouse - INPT (FRANCE)
French research institutions > Centre National de la Recherche Scientifique - CNRS (FRANCE)
Université de Toulouse > Université Toulouse III - Paul Sabatier - UPS (FRANCE)
Université de Toulouse > Université Toulouse - Jean Jaurès - UT2J (FRANCE)
Université de Toulouse > Université Toulouse 1 Capitole - UT1 (FRANCE)
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Deposited By: IRIT IRIT
Deposited On:23 Jun 2015 13:47

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